IMUL (Signed Multiply)

Opcodes

Opcode Instruction Op/En 64-Bit Mode Compat/Leg Mode Description
F6 /5 IMUL r/m8* M Valid Valid AX← AL ∗ r/m byte.
F7 /5 IMUL r/m16 M Valid Valid DX:AX ← AX ∗ r/m word.
F7 /5 IMUL r/m32 M Valid Valid EDX:EAX ← EAX ∗ r/m32.
REX.W + F7 /5 IMUL r/m64 M Valid N.E. RDX:RAX ← RAX ∗ r/m64.
0F AF /r IMUL r16, r/m16 RM Valid Valid word register ← word register ∗ r/m16.
0F AF /r IMUL r32, r/m32 RM Valid Valid doubleword register ← doubleword register ∗ r/m32.
REX.W + 0F AF /r IMUL r64, r/m64 RM Valid N.E. Quadword register ← Quadword register ∗ r/m64.
6B /r ib IMUL r16, r/m16, imm8 RMI Valid Valid word register ← r/m16 ∗ sign-extended immediate byte.
6B /r ib IMUL r32, r/m32, imm8 RMI Valid Valid doubleword register ← r/m32 ∗ sign-extended immediate byte.
REX.W + 6B /r ib IMUL r64, r/m64, imm8 RMI Valid N.E. Quadword register ← r/m64 ∗ sign-extended immediate byte.
69 /r iw IMUL r16, r/m16, imm16 RMI Valid Valid word register ← r/m16 ∗ immediate word.
69 /r id IMUL r32, r/m32, imm32 RMI Valid Valid doubleword register ← r/m32 ∗ immediate doubleword.
REX.W + 69 /r id IMUL r64, r/m64, imm32 RMI Valid N.E. Quadword register ← r/m64 ∗ immediate doubleword.

NOTES:

*

In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.

Instruction Operand Encoding

Op/En Operand 1 Operand 2 Operand 3 Operand 4
M ModRM:r/m (r, w) NA NA NA
RM ModRM:reg (r, w) ModRM:r/m (r) NA NA
RMI ModRM:reg (r, w) ModRM:r/m (r) imm8/16/32 NA

Description

Performs a signed multiplication of two operands. This instruction has three forms, depending on the number of operands.

When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.

The CF and OF flags are set when the signed integer value of the intermediate product differs from the sign extended operand-size-truncated product, otherwise the CF and OF flags are cleared.

The three forms of the IMUL instruction are similar in that the length of the product is calculated to twice the length of the operands. With the one-operand form, the product is stored exactly in the destination. With the two- and three- operand forms, however, the result is truncated to the length of the destination before it is stored in the destination register. Because of this truncation, the CF or OF flag should be tested to ensure that no significant bits are lost.

The two- and three-operand forms may also be used with unsigned operands because the lower half of the product is the same regardless if the operands are signed or unsigned. The CF and OF flags, however, cannot be used to determine if the upper half of the result is non-zero.

In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to addi-tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. Use of REX.W modifies the three forms of the instruction as follows.

Operation

IF (NumberOfOperands = 1)
    THEN IF (OperandSize = 8)
         THEN
              TMP_XP ← AL ∗ SRC (* Signed multiplication; TMP_XP is a signed integer at twice the width of the SRC *) ;
              AX ← TMP_XP[15:0];
              SF ← TMP_XP[7];
              IF SignExtend(TMP_XP[7:0]) = TMP_XP
                    THEN CF ← 0; OF ← 0;
                    ELSE CF ← 1; OF ← 1; FI;
         ELSE IF OperandSize = 16
              THEN
                    TMP_XP ← AX ∗ SRC (* Signed multiplication; TMP_XP is a signed integer at twice the width of the SRC *)
                    DX:AX ← TMP_XP[31:0];
                    SF ← TMP_XP[15];
                    IF SignExtend(TMP_XP[15:0]) = TMP_XP
                         THEN CF ← 0; OF ← 0;
                         ELSE CF ← 1; OF ← 1; FI;
              ELSE IF OperandSize = 32
                    THEN
                         TMP_XP ← EAX ∗ SRC (* Signed multiplication; TMP_XP is a signed integer at twice the width of the SRC*)
                         EDX:EAX ← TMP_XP[63:0];
                         SF ← TMP_XP[32];
                         IF SignExtend(TMP_XP[31:0]) = TMP_XP
                              THEN CF ← 0; OF ← 0;
                              ELSE CF ← 1; OF ← 1; FI;
                    ELSE (* OperandSize = 64 *)
                         TMP_XP ← RAX ∗ SRC (* Signed multiplication; TMP_XP is a signed integer at twice the width of the SRC *)
                         EDX:EAX ← TMP_XP[127:0];
                         SF ← TMP_XP[63];
                         IF SignExtend(TMP_XP[63:0]) = TMP_XP
                              THEN CF ← 0; OF ← 0;
                              ELSE CF ← 1; OF ← 1; FI;
                    FI;
         FI;
    ELSE IF (NumberOfOperands = 2)
         THEN
              TMP_XP ← DEST ∗ SRC (* Signed multiplication; TMP_XP is a signed integer at twice the width of the SRC *)
              DEST ← TruncateToOperandSize(TMP_XP);
              SF ← MSB(DEST);
              IF SignExtend(DEST) ≠ TMP_XP
                    THEN CF ← 1; OF ← 1;
                    ELSE CF ← 0; OF ← 0; FI;
         ELSE (* NumberOfOperands = 3 *)
              TMP_XP ← SRC1 ∗ SRC2 (* Signed multiplication; TMP_XP is a signed integer at twice the width of the SRC1 *)
              DEST ← TruncateToOperandSize(TMP_XP);
              SF ← MSB(DEST);
              IF SignExtend(DEST) ≠ TMP_XP
                    THEN CF ← 1; OF ← 1;
                    ELSE CF ← 0; OF ← 0; FI;
    FI;
FI;

Flags Affected

SF is updated according to the most significant bit of the operand-size-truncated result in the destination. For the one operand form of the instruction, the CF and OF flags are set when significant bits are carried into the upper half of the result and cleared when the result fits exactly in the lower half of the result. For the two- and three-operand forms of the instruction, the CF and OF flags are set when the result must be truncated to fit in the destination operand size and cleared when the result fits exactly in the destination operand size. The ZF, AF, and PF flags are undefined.

Protected Mode Exceptions

#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL NULL segment selector.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UD If the LOCK prefix is used.

Real-Address Mode Exceptions

#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS If a memory operand effective address is outside the SS segment limit.
#UD If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0) If a memory operand effective address is outside the SS segment limit.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made.
#UD If the LOCK prefix is used.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0) If a memory address referencing the SS segment is in a non-canonical form.
#GP(0) If the memory address is in a non-canonical form.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UD If the LOCK prefix is used.